PANCIONI LUCA
Office hours
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Wednesday from 16:00 to 18:00Place: Ufficio 235
Teaching activities
Completion accademic year: 2025/2026
Course year: 1
Second cycle degree (Laurea Magistrale)
ELECTRONICS AND COMMUNICATIONS ENGINEERING
A.Y. 2025/2026
Course year: 2
Second cycle degree (Laurea Magistrale)
ELECTRONICS AND COMMUNICATIONS ENGINEERING
A.Y. 2024/2025
Course year: 3
First cycle degree (DM 270)
INGEGNERIA INFORMATICA E DELL'INFORMAZIONE
A.Y. 2023/2024
Completion accademic year: 2024/2025
Course year: 1
Second cycle degree (Laurea Magistrale)
ELECTRONICS AND COMMUNICATIONS ENGINEERING
A.Y. 2024/2025
Course year: 3
First cycle degree (DM 270)
INGEGNERIA INFORMATICA E DELL'INFORMAZIONE
A.Y. 2022/2023
Completion accademic year: 2023/2024
Course year: 1
Second cycle degree (Laurea Magistrale)
ELECTRONICS AND COMMUNICATIONS ENGINEERING
A.Y. 2023/2024
Research
Ultime pubblicazioni:
- Di Marco, M., Forti, M., Pancioni, L., Innocenti, G., Tesi, A. (In corso di stampa). Extreme Multistability of Memristor Circuits Operating in the Complex Domain. INTERNATIONAL JOURNAL OF BIFURCATION AND CHAOS IN APPLIED SCIENCES AND ENGINEERING [10.1142/s0218127426300065]. - view more
- Di Marco, M., Forti, M., Pancioni, L., Innocenti, G., Tesi, A. (In corso di stampa). Robust Convergence in a Class of Nonlinear Circuits With Memristors. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS, 1-14 [10.1109/tcsi.2025.3641690]. - view more
- Innocenti, G., Tesi, A., Di Marco, M., Pancioni, L., Forti, M. (2025). Feature preserving discretization of memristive circuits using an input-output approach. NONLINEAR DYNAMICS, 113(20), 28179-28206 [10.1007/s11071-025-11568-4]. - view more
- Di Marco, M., Forti, M., Pancioni, L., Innocenti, G., Tesi, A. (2025). Memristor Circuits as Linear-Gradient Systems and Discrete Analogues Preserving a First Integral. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS, 72(10), 5984-5997 [10.1109/tcsi.2025.3554341]. - view more
- Di Marco, M., Forti, M., Pancioni, L., Innocenti, G., Tesi, A. (2024). Embedding classic chaotic maps in simple discrete-time memristor circuits. IEEE ACCESS, 12, 148216-148229 [10.1109/ACCESS.2024.3474801]. - view more