Orari di ricevimento

  • Lunedi' dalle 09:00 alle 10:00
    Luogo: Edificio S. Niccolo', Via Roma n.56 - stanza 231
    Nota: previo appuntamento e-mail

Attività di ricerca

Ultime pubblicazioni:

  • Zhang, Y., Khayatzadeh, M., Yang, K., Saligane, M., Pinckney, N., Alioto, M., et al. (2018). IRazor: Current-Based Error Detection and Correction Scheme for PVT Variation in 40-nm ARM Cortex-R4 Processor. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 53(2), 619-631. - dettaglio
  • Taneja, S., Alvarez, A.B., & Alioto, M. (2018). Fully Synthesizable PUF Featuring Hysteresis and Temperature Compensation for 3.2% Native BER and 1.02 fJ/b in 40 nm. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 53(10), 2828-2839. - dettaglio
  • Alvarez, A.B., Zhao, W., & Alioto, M. (2016). Static Physically Unclonable Functions for Secure Chip Identification With 1.9-5.8% Native Bit Instability at 0.6-1 V and 15 fJ/bit in 65 nm. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 51(3), 763-775. - dettaglio
  • Alioto, M., Consoli, E., & Palumbo, G. (2015). Variations in nanometer CMOS flip-flops: Part i - Impact of process variations on timing. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS, 62(8), 2035-2043. - dettaglio
  • Elio, C., Gaetano, P., Jan M., R., & Alioto, M.B.C. (2014). Novel Class of Energy-Efficient Very High-Speed Conditional Push–Pull Pulsed Latches. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 22, 1593-1605. - dettaglio