ALIOTO MASSIMO BRUNO CRIS

Orari di ricevimento

  • Lunedi' dalle 09:00 alle 10:00
    Luogo: Edificio S. Niccolo', Via Roma n.56 - stanza 231
    Nota: previo appuntamento e-mail

Attività di ricerca

Ultime pubblicazioni:

  • Fabio, F., Mahmood, K., David, B., Dennis, S., & Alioto, M.B.C. (2014). 13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC). In 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) (pp.244-245). - dettaglio
  • Wenfeng, Z., Yajun, H.a., & Alioto, M.B.C. (2014). Novel Self-Body-Biasing and Statistical Design for Near-Threshold Circuits With Ultra Energy-Efficient AES as Case Study. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1-1. - dettaglio
  • Alioto, M.B.C., Simone, B., Giuseppe, S., & Alessandro, T. (2014). Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES). In 2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES) (pp.241-246). - dettaglio
  • Alioto, M.B.C., Simone, B., Milena, D., Giuseppe, S., & Alessandro, T. (2014). Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS. I, REGULAR PAPERS, 61, 429-442. - dettaglio
  • David, E., Manuel, G., Bernard, K., Tommaso, R., & Alioto, M.B.C. (2014). Tunnel FETs for Ultralow Voltage Digital VLSI Circuits: Part I-Device-Circuit Interaction and Evaluation at Device Level. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 1-1. - dettaglio